The performance of modem integrated circuits is often limited by power consumption considerations. Integrated circuits often use complementary metal-oxide semiconductor (CMOS) transistor technology such as n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistors.
Typically, NMOS and PMOS integrated circuits have four terminals—a drain, a source, a gate, and a body. The body terminal, which is sometimes referred to as the well or bulk terminal, can be biased to improve transistor performance. For example, a positive bias voltage can be applied to the body of a PMOS transistor and a negative bias voltage can be applied to the body of an NMOS transistor. The implementation should be such that the body bias voltages should be regulated besides supplying the load current. The load current here is the leakage current of P-well and N-well. These bias voltages increase the effective threshold voltages of the transistors and thereby reducing their leakage currents. Any reductions in the leakage current can also reduce power consumption.
Body bias voltages tend to be a small value. For example, an NMOS body bias voltage may be less than a few hundred millivolts. Larger body bias voltages can be used to reduce the leakage current further, however, may have a significant adverse impact on a device performance. The optimum balance between the reduced leakage current and sacrificed performance is generally obtained using small body bias voltages. Generally, body bias voltages can be generated off chip, however, this approach may consume already limitedly available number of input-output pins in the integrated circuit.
Existing methods for generating body bias voltage use regulated charge pumps. In these methods, the regulation of power supply voltage requires turning the charge pumps ON and OFF to maintain the output voltages within a desired ripple. This approach requires a capacitor at the output of the charge pump otherwise it can result in a higher ripple voltage.
The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.